The present invention relates to the clock synchronous circuit which is used in semiconductor devices, such as double data rate synchronous DRAM, especially to the clock synchronous circuit suitable for such devices as those which perform synchronous control by using a high-speed clock.
In recent years, clock synchronous type memories, such as synchronous DRAM, are used in computer systems, reflecting demands for high-speed processing. Such a clock synchronous type memory utilizes the clock, which synchronizes with the clock supplied from the outside of the memory (to be referred to as the external clock hereinafter) to control internal operation, by generating it inside the memory.
In case a synchronous lag takes place between the clock used inside the memory (to be referred to as the internal clock hereinafter) and the external clock, it will be liable to cause mis-operation in the internal circuit of the memory especially in high-speed processing even if the lag is very small. Furthermore, the use of the internal clock, which has a synchronous lag arising between it and the external clock, hinders high-speed operation on the side of the controller using data read from the memory.
Thus recent memories are beginning to be mounted with clock synchronous circuits which are designed to synchronize the internal clock to the external clock with high precision.
However, while memories mounted with clock synchronous circuits are capable of performing stable high-speed operation, their power consumption become larger correspondingly, compared with the memories which are not mounted with clock synchronous circuits.
In order to reduce such a disadvantage, it is desired to reduce power consumption by halting the operation of the clock synchronous circuit as far as possible when the internal circuit of the memory does not require the internal clock outputted from the clock synchronous circuit.
However, conventional clock synchronous circuits are not capable of reducing power consumption in actual practice even by halting the operation because they have no established methods for halting and controlling the operation nor established halt control circuits.